The S-R latch is a key circuit in digital storage units. In this tutorial, you will learn how it works, its truth table, and how to build one with different logic gates.
What is an S-R Latch?
Before starting with the S-R latch you need to know what a latch is. A latch is an asynchronous circuit (it doesn’t require a clock signal to work), and it has two stable states, HIGH (“1”) and LOW (“0”), that can be used for storing binary data. Many sequential circuits and larger storage devices, such as shift registers, use latches as their principal building block.
The simplest latch is the Set-Reset (S-R) latch. You can build one by connecting two NOR gates with a cross-feedback loop.
This feedback path is crucial to storing one bit of data as long as the circuit is powered. In this circuit, the upper gate has the S input and the main output Q, while the lower gate has the R input and the inverted output Q̅.
How does the S-R Latch work?
First of all, let’s define the truth table of the S-R latch:
| Input S | Input R | Output Q |
|---|---|---|
| 0 | 0 | Previous State |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 0 (Invalid) |
Now, let’s analyze how the S-R latch works using its truth table and its circuit with NOR gates. Remember that the NOR gate only gives “1” when both inputs are “0”, with any other input combination the output is “0”.
You can see in the truth table that when both inputs S and R are equal to “0”, the output Q remains the same as it was. This is the memory function of the S-R latch because it saves the previous value. Suppose the Q output is “1” in the present state. If you now place both inputs in “0”, then the output will remain “1” as follows:
Then, how would you “Reset” the Q output to “0”? Well, as you can see in the truth table, you need a “1” in the R input and a “0” in the S input.
But, if you want to “Set” a “1” in the Q output just follow the truth table and place a “1” in the S input and a “0” in the R input.
Finally, the S and R inputs should never be “1” at the same time because the NOR gate only gives “1” when both of its inputs are “0”, but if one input is “1”, then the output will be “0”. As a result, if S and R are “1”, both latches’ outputs will be “0” at the same time, something that violates this latch’s working principle.
SR-LATCH WITH NAND GATES
The S-R Latch can also be built using two NAND gates:
In the above circuit, you might have noticed slight differences from the one with NOR gates. Now the inputs have been swapped, with the S input in the upper gate and the R input in the lower gate. In addition, the inputs have been negated.
It works the same way as with NOR gates, just that the inputs are inverted. Here’s the truth table:
| Input S | Input R | Output Q |
|---|---|---|
| 1 | 1 | Previous State |
| 1 | 0 | 0 |
| 0 | 1 | 1 |
| 0 | 0 | 0 (Invalid) |
Example Circuit
As a practical example, you can build an SR latch using the CD4001 chip. Below you can see how the CD4001 has four NOR gates inside, making it ideal for this kind of application.
The circuit works as follows: when the button PB2 is pushed, the LED L2 turns on and stays on even after PB2 is released, while the LED L1 remains off. LED L2 turns off when the button PB1 is pressed, whereas LED L1 turns and stays on even after PB1 has been released. To assemble the above circuit you need:
- The CD4001 chip
- Two push buttons (PB1 and PB2)
- Two LEDs
- Two 10 kΩ resistors (R1 and R2)
- Two 330 Ω resistors (R3 and R4)
Questions?
Do you have any questions about S-R Latch? Let me know in the comments below.
In the provided example circuit, what happens when you press both buttons, thus triggering the invalid state? Is there risk of damaging the circuit?
You don’t damage anything, no. In the circuit example above, both outputs will be 0 if you push both buttons.
So there won’t be instability due to the feedback? I suppose that this is why you’ve mentioned it as an invalid state. Are there any drawbacks to being in this invalid state?
There’s no instability, it’s just that both outputs become 0.
It’s invalid because when you stop pushing the buttons, the resulting value depends on which button you released first. Even if you try to release them at the same time, there will be a tiny difference, and this difference decides what the next output will be.
So you want to avoid doing that.
Hi, I have a question for you. At the beginning that finished circuit with a power voltage applied. All R and S input has a LOW stage. So what are the stages of Q and not Q in the beginning?